1. Field of the Invention
The present invention is generally directed to microprocessor devices. In particular, the present invention relates to microprocessor devices which constitute a System-on-a-Chip (SoC), including but not limited to SoC implementations of a multiprocessor system.
2. Background
Conventional System-on-a-Chip (SoC) implementations utilize large static on-chip memories to meet their memory needs. This memory may potentially be shared among several processors running multiple processes. Given the complexity of combining very large memories on an integrated circuit (IC) with one or more processors, the amount of storage space in these memories may be limited. The conventional solution is to provide the SoC with an even larger off-chip memory in order to meet its memory demands, and treating the on-chip memory as a cache. The downside of this approach is that when a process requests data from the cache which it does not have a copy of, the entire processor must stall while the cache memory goes to the off-chip memory to retrieve a copy of the information. The delays associated with such off-chip memory retrieval are substantial, and not conducive to real-time processing.
Accordingly, what is desired is a system and method that resolves the problem of delays associated with off-chip memory retrieval.